Thesis Overview: Reducing Branch Misprediction Penalty through Confidence Estimation

Control dependences are one of the major limitations to increase the performance of current processors. A branch instruction supposes an interruption of the sequential flow of instructions traversing the pipeline because the next instruction address is unknown until the branch is executed. However, the fetch stage should introduce the successor instruction following the branch as soon as possible in order to maximize processor performance. Control speculation is employed in order to achieve this goal, predicting the outcome of the branch, guessing the successor address and speculatively starting the execution of those instructions from the predicted path. But despite the important benefits provided by branch prediction schemes, there are many mispredicted branches. This means that the pipeline is filled with many wrong path instructions, being necessary flushing the pipeline and restoring the correct state of the processor.